Relentless demand for further device integration in semiconductor devices requires ever narrower spacing between device configurations. Taking a NAND flash memory for example, bit line widths and gaps between the bit lines in the memory cell region are becoming narrower with time. Thus technical challenge increases in forming narrower opening patterns in lithography processing of configurations such as contact holes and via holes.
One exemplary solution to address such technical difficulty is disclosed in a via hole processing illustrated in FIG. 2 of JP H10-233445 A in which an opening pattern is defined on an insulating film which is wide enough to be processed by lithography, whereafter the opening is narrowed to reduce its surface area by forming a spacer on the inner upper end wall of the via hole.
The disclosed method, however has the following problems.
When filling the contact hole with conductive material, a void may occur in the resulting contact plug. When a via hole is opened by etching through an overlying layer to reach the upper surface of the contact plug, the void residing in the proximity of the upper surface of the contact plug may be opened up. When an insulating films is formed as a spacer on the inner wall of the via hole under such state for shrinking the width of the via hole, the insulating film may be introduced into the opened up void and remain unremoved to cause conduction failures.